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ARM Cortex-M Knowledge Assessment Quiz

Test Your Embedded Systems and Microcontroller Skills

Difficulty: Moderate
Questions: 20
Learning OutcomesStudy Material
Colorful paper art depicting a quiz on ARM Cortex-M Knowledge Assessment

Get ready to power up your embedded systems expertise with this ARM Cortex-M Knowledge Assessment quiz crafted for engineers and students alike. This microcontroller quiz dives into architecture, interrupt handling, memory mapping, and low-power modes to sharpen your technical prowess. It's fully customizable in our user-friendly editor, letting you adapt questions to your course or training session. Check out our Basic Knowledge Assessment Quiz or tackle the IT Knowledge Assessment Quiz for additional challenge. Discover more quizzes to continue honing your skills.

Which instruction set do ARM Cortex-M processors use?
MIPS
Thumb
ARM
PowerPC
ARM Cortex-M cores execute the Thumb instruction set, which is a compact 16/32-bit instruction set. This allows for more efficient code density and performance. They do not support the full 32-bit ARM or other ISAs.
How many general-purpose registers (R0 - R12) does the Cortex-M core provide?
16
12
13
8
The Cortex-M core includes R0 through R12, giving a total of 13 general-purpose registers. These are used for arithmetic, data movement, and addressing operations. Additional special registers include SP, LR, PC, and PSR.
What is the base address of the SRAM region in the Cortex-M memory map?
0x40000000
0x20000000
0x08000000
0x00000000
In the ARM Cortex-M memory map, SRAM is located starting at address 0x20000000. Flash memory typically starts at 0x08000000 and peripherals at 0x40000000. The 0x00000000 region is aliased to the code space.
What does NVIC stand for in Cortex-M architectures?
Networked Vector Interrupt Core
Nested Vectored Interrupt Controller
Numerical Vector Integration Circuit
Non-Volatile Interrupt Configurator
NVIC stands for Nested Vectored Interrupt Controller. It provides nested interrupt handling with programmable priorities. This block is integral to the Cortex-M exception system.
Which register number corresponds to the program counter in Cortex-M cores?
R14
R15
R12
R13
In the ARM architecture, R15 is the program counter (PC) register. It always contains the address of the instruction being executed. R13 is the stack pointer and R14 is the link register.
In Cortex-M3, which bus is primarily used for peripheral and memory data accesses?
APB bus
System bus
I-Code bus
D-Code bus
The Cortex-M3 features separate I-Code and System buses. The System bus handles data transfers to memory and peripherals, while the I-Code bus is dedicated to instruction fetches. The APB is part of the peripheral interconnect, not the core bus matrix.
During exception entry, which registers are automatically pushed onto the stack?
LR, PC only
R0 - R7
R4 - R11
R0 - R3, R12, LR, PC, xPSR
On exception entry, the hardware automatically stacks R0 - R3, R12, LR, PC, and xPSR. This allows the handler to use these registers and later return correctly. Other registers must be saved by software if needed.
In the NVIC interrupt prioritization, how does a lower numerical priority value relate to interrupt urgency?
It indicates a higher priority
It has no effect
It disables priority grouping
It indicates a lower priority
In the NVIC, a lower numerical priority value corresponds to a higher interrupt priority. Thus, Priority 0 is the highest urgency. This scheme allows fine-grained priority configuration.
Which register and bit in the System Control Block (SCB) selects deep sleep mode on Cortex-M?
SCR.SLEEPONEXIT bit
CONTROL.SLEEPDEEP bit
AIRCR.SYSRESETREQ bit
SCR.SLEEPDEEP bit
The SLEEPDEEP bit in the SCB System Control Register (SCR) selects between sleep and deep sleep modes. Setting this bit causes the core to enter the deeper power-down state on a WFI instruction. SLEEPONEXIT is a different bit that controls return behavior.
What instruction suspends core execution until the next interrupt arrives?
SVC
WFI
WFE
NOP
The WFI (Wait For Interrupt) instruction places the core in sleep mode until an interrupt occurs. WFE (Wait For Event) waits for an event signal instead. NOP does nothing and SVC triggers a software interrupt.
In the CONTROL register, which bit determines the active stack pointer?
Bit 3
Bit 2
Bit 0
Bit 1
CONTROL bit 1 selects the stack pointer: 0 for Main Stack Pointer (MSP) and 1 for Process Stack Pointer (PSP). Bit 0 controls privilege level. Bits 2 and 3 are reserved or implementation-defined.
Which debug interface for Cortex-M uses only two signal lines?
SWD
ETM
JTAG
SWO
SWD (Serial Wire Debug) uses two lines: SWCLK and SWDIO. JTAG uses multiple pins (TCK, TMS, TDI, TDO, TRST). ETM (Embedded Trace Macrocell) and SWO (Single Wire Output) are trace interfaces, not full debug ports.
How many pipeline stages are implemented in a Cortex-M3 core?
3
2
4
5
The Cortex-M3 core uses a three-stage pipeline: Fetch, Decode, and Execute. This balances performance and simplicity. Cortex-M0 cores use a simpler two-stage pipeline.
Which type of memory access is not directly supported by the Cortex-M execution model?
Memory-to-memory
Load/store
Register-to-register
Atomic
Cortex-M implements a load/store architecture, meaning all data operations must go through registers. There are no direct memory-to-memory operations. Atomic operations require special instructions or hardware support.
Which SCB register holds the base address of the interrupt vector table?
ICSR
SHCSR
AIRCR
VTOR
The Vector Table Offset Register (VTOR) in the System Control Block specifies the base address of the interrupt vector table. This allows relocation of the table in memory. ICSR handles pending interrupts, AIRCR controls system resets, and SHCSR manages system handlers.
Which barrier instruction ensures completion of all explicit memory accesses before subsequent instructions?
DSB
DMB
WFE
ISB
The DSB (Data Synchronization Barrier) instruction ensures that all explicit memory accesses have completed before any following instructions execute. A DMB (Data Memory Barrier) only orders memory operations but does not wait for completion. ISB flushes the pipeline, and WFE waits for events.
In the Cortex-M MPU, what is the minimum configurable region size?
256 bytes
1 KB
32 bytes
8 bytes
The Cortex-M Memory Protection Unit supports a minimum region size of 32 bytes, with sizes increasing in powers of two. Regions smaller than this are not allowed. This granularity balances flexibility and overhead.
What is the maximum reload value for the 24-bit SysTick timer?
0xFFFFFF
0xFFFFFFFF
0xFFFF
0xFFFFF
SysTick provides a 24-bit reload register, so its maximum value is 0xFFFFFF (16,777,215). Values larger than 24 bits are truncated. A 32-bit reload value (0xFFFFFFFF) is not supported.
The SWD debug interface omits which JTAG signal?
TCK
TDO
TDI
TRST
SWD replaces the JTAG TCK and TMS signals with a single clock (SWCLK) and data line (SWDIO), and it omits the TRST pin entirely. TDI and TDO functionality are also multiplexed over SWDIO. SWD therefore reduces pin count.
When relocating the vector table using VTOR, the base address must be aligned to what boundary?
256 bytes
32 bytes
128 bytes
64 bytes
The VTOR register requires the vector table base address to be aligned to at least 128-byte boundaries. The lower 7 bits of VTOR must be zero. This alignment is mandated to ensure proper exception entry behavior.
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Learning Outcomes

  1. Analyse ARM Cortex-M processor architecture and features
  2. Identify core registers, memory maps, and bus systems
  3. Evaluate exception handling and interrupt priorities
  4. Apply power management and low-power modes effectively
  5. Demonstrate knowledge of instruction set and execution model
  6. Master debugging and programming workflow for Cortex-M

Cheat Sheet

  1. Understand the ARM Cortex-M Processor Architecture - Dive into the world of ARMv6-M, ARMv7-M and ARMv8-M cores to see how each generation builds on the last with new instructions, improved performance and better power efficiency. You'll get a big-picture view of why Thumb-2 is a game-changer for balancing speed and code size. Read more
  2. Identify Core Registers and Their Functions - Meet the registers that run the show: R0 - R12 for general tasks, plus SP (stack pointer), LR (link register) and PC (program counter). You'll also unlock the secrets of the status registers that tell the CPU how things are going at any moment. Read more
  3. Explore the Memory Map and Bus System - Picture your code, SRAM, peripherals and system control areas laid out like a city map. Learn how the bus system acts like highways and side streets, moving data between the CPU and peripherals without traffic jams. Read more
  4. Grasp Exception Handling and Interrupt Priorities - Interrupts are like urgent messages that can pause your program anytime - NVIC is the postmaster that decides who's next. Master priority levels and stacking rules so you can keep your system responsive and crash-proof. Read more
  5. Implement Power Management and Low-Power Modes - Discover Sleep, Deep Sleep and other modes that let your device nap when it's not working hard. You'll learn tricks to stretch battery life without waking up the chip more than necessary. Read more
  6. Master the Instruction Set and Execution Model - Get hands-on with Thumb-1 and Thumb-2 instructions to see how they pack more punch into fewer bytes. Peek inside the pipeline stages - fetch, decode, execute - and learn why understanding them makes your code faster and leaner. Read more
  7. Utilize Debugging and Programming Tools - From JTAG and SWD to the Micro Trace Buffer (MTB), these tools are your best friends when hunting bugs. Learn how to set breakpoints, step through code and trace execution paths like a digital detective. Read more
  8. Understand the Role of the Memory Protection Unit (MPU) - Think of the MPU as a security guard for your memory regions, enforcing who can read, write or execute which sections. It's a key feature for preventing errant code from trashing important data. Read more
  9. Explore the Use of Bit-Banding - Bit-banding turns a whole 32-bit word into an array of single bits you can flip on or off directly. This clever trick makes toggling peripheral registers lightning-fast and atomic. Read more
  10. Study the Floating-Point Unit (FPU) Options - Some Cortex-M cores sport single-precision or even double-precision FPUs that turbocharge math operations. Perfect for DSP or control systems where precision matters, they save you from wrestling with slow software routines. Read more
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